1. Field of the Invention
The invention generally relates to a memory system, and more particularly, to a data reading method with optimal error bit correction capability, and a memory controller and a memory storage device using the same.
2. Description of Related Art
Existing flash memories can be categorized into NOR flash memories and NAND flash memories. NAND flash memory has two different storage modes: a multi-level cell (MLC) storage mode and a single-level cell (SLC) storage mode. In the SLC storage mode, one data bit is stored in each memory cell. While in the MLC storage mode, two or more data bits are stored in each memory cell.
Generally speaking, while writing data into or reading data from a specific memory cell in a memory cell array connected by bit lines and word lines, memory cells other than the specific memory cell are disturbed, and accordingly the threshold voltage for writing data into these memory cells are changed. In addition, wear caused by long-term idle, electric leakage, or repeated erasing or programming operations may also change the threshold voltage for writing data into a memory cell. Thus, errors may occur when a written data is read.
On the other hand, a memory storage device needs to adopt an error correcting technique (for example, the low density parity check code (LDPC code) technique) with optimal error correction capability to perform an error checking and correcting (ECC) procedure on data. The memory storage device obtains a log likelihood ratio (LLR) corresponding to soft information according to a lookup table stored in the memory storage device and then performs an error correcting operation by using a LDPC code. However, the error characteristics of a rewritable non-volatile memory in the memory storage device change with the increase of erase-program times. Accordingly, in order to obtain the optimal LLR, the error characteristics of the rewritable non-volatile memory have to be constantly determined. As a result, the load of the system will be drastically increased.
Nothing herein should be construed as an admission of knowledge in the prior art of any portion of the present invention. Furthermore, citation or identification of any document in this application is not an admission that such document is available as prior art to the present invention, or that any reference forms a part of the common general knowledge in the art.